In a semiconductor memory device, memory cells may be susceptible to errors based on a transient error or a soft error. The errors may be due to a transient error caused by noises from surrounding components in the device with high-density. Soft errors may be caused by background radiation. The semiconductor memory device may execute a test mode for dynamic random access memory (DRAM), in order to detect and correct errors. For example, memories have been developed that include redundant rows or columns to replace defective memory cells with errors.
For example, a semiconductor memory device may support fail row address repair, so called Post Package Repair (PPR) that is a hard repair of one fail row per memory bank (hereinafter, “bank”) using antifuses. For example, an antifuse may have a high resistance in its initial state, and can permanently create an electrically conductive path (“blow an antifuse”) when a relatively high voltage is applied across the antifuse. For example, an antifuse can have a structure similar to that of a capacitor, i.e., two conductive electrical terminals are separated by a dielectric layer, that may be broken down by blowing the antifuse.
Additionally, Soft Post Package Repair (SPPR) for repair of one row per bank may be supported. Soft post package repair can refer to a non-persistent method of post package repair. In soft post package repair, defective address data can be stored in volatile memory of the semiconductor memory device after the memory device is packaged. The defective address data can, for example, correspond to a group of memory cells that were identified as defective post packaging. In some cases, the group of memory cells identified as defective post packaging could be a group of redundant memory cells to which an address has been previously remapped. In such cases, other defective address data can already be stored in programmable elements, such as antifuses, so that memory cells associated with the other defective address data are not accessed. The defective address data can be stored as part of a power-up sequence of a semiconductor memory device, for example. The defective address data can be stored in volatile memory until the semiconductor memory device is powered down. A storage element comprising volatile memory, such as latches, registers, and/or flip-flops, can store the defective address data and a decoder can map the defective address to another group of memory cells. The other group of memory cells can be a group of redundant memory cells (e.g., a column or row of redundant memory cells) that are dedicated to soft post package repair.
Typically, a conventional semiconductor memory device (e.g., LPDDR4) may include standard antifuses that are dedicated to the PPR functionality, as the PPR has been used for permanent repair of a defective row by blowing a corresponding antifuse. Registers for the SPPR may be separately provided, since performing the SPPR is optional after performing the PPR. Performing the PPR and the SPPR may require a lot of storage space for antifuses and registers, and an effective array usage method may be desired to improve a yield on a wafer.